Job Detail

What You'll Do

You'll be joining a team of world-class circuit designers and will work on communication circuits using state-of-the art CMOS FinFet technologies with feature sizes of 7nm and below. 

You will be responsible for the layout and layout methodology of high-performance mixed-mode analog-digital circuits operating at high-frequencies. You will develop design techniques and best practices to master these layouts, which now became one of the biggest challenges in high-speed circuit design.

Who You'll Work With

The team you will work with has an outstanding history in delivering innovative ideas and world-leading circuit solutions in silicon. The team has a long track-record of publications and contributions to products, and highly recognizes optimized layout design as being a key enabler for leading circuit performance.

Also, you'll be part of our Group driving our game changing next generation network devices - Cisco Silicon One™. We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One™ is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

 Learn more about us right here:

www.cisco.com/c/en/us/solutions/service-provider/innovation/silicon-one.html

www.en.greatplacetowork.ch/workplace/item/982/Cisco+Systems+%28Switzerland%29+GmbH

fortune.com/2019/12/11/cisco-ceo-chuck-robbins-chips/?_lrsc=ce750ac5-11c8-4995-bfd3-936de1c06009&dtid=osolin001080

www.youtube.com/watch?v=iy8259BGg6U

Who You Are

We are looking for exceptional individuals to join our team:

Minimum Qualifications:

• Electrical Engineerwith B.Sc in EE from University or Applied University (Fachhochschule)


• Custom analog and mixed signal layout expertise in CMOS, ideally with experience in 16nm, 7nm or smaller CMOS FinFet technology


• You should be eager to learn and succeed!


• Good team player


• Expertise with Cadence Virtuoso CAD design environment– including custom layout, DRC, LVS, and parasitic extraction

Advantageous:

• Experience with other CAD tools (Mentor, Synopsis)


• Experience with coil design using EM field simulator such as Momentum or HFSS


• Programming skills with: Skill, Tcl, Perl, Python, Matlab, C


• Knowledge of P&R tools and P-Cell design

Why Cisco

We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns. 

Cisco is a leader in corporate social responsibility and puts a major emphasis on fostering a healthy company culture within its organization. Cisco was ranked the #1 best place to work in the world by Great Places to Work in 2019. In addition, in 2018 Cisco was ranked the #1 best place to work in Switzerland.

#WeAreCisco



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Please note this posting is to advertise potential job opportunities. This exact role may not be open today, but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.